A 3D package contains two or more integrated circuits (ICs) stacked vertically so that they occupy less space. Connections between the vertically stacked ICs may be made using through-silicon-vias (TSV), which pass through the entire thickness of a die, permitting connections between conductive patterns on the front face and back face of the die. The resulting package has no added length or width. Because no interposer is required, a 3D package using TSVs can be flatter than an edge-wired 3D package.
For 3D IC, power TSV are typically used for transferring power. The processing steps to form TSVs increase the cost of fabricating the IC. In addition, there is an area penalty for adding these TSVs, because the space occupied by the TSVs cannot be used for any other circuitry.
An alternative packaging technique is the so called “2.5D IC”, in which plural IC chips are mounted on a silicon interposer. The interconnections between the various functional ICs and the silicon interposer are made using microbumps (μ-bumps), which are typically on the order of 15-50 micrometers. The μ-bumps are much smaller and more fragile than the solder bumps which are used to join an IC directly to a package substrate. During wafer acceptance test and/or individual die testing, the μ-bumps may be directly accessed by a probe card for testing. There is thus a potential for the μ-bumps to be damaged.